Srbija Posted October 27, 2022 Share #1 Posted October 27, 2022 System Design Using Verilog Last updated 8/2022 MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz Language: English | Size: 16.09 GB | Duration: 28h 48m FPGA Based Design What you'll learn Verilog coding for digital circuits Requirements No Description After completion of this course learners will be able to:(1) Understand the concepts design metrics which are to be optimized by a design engineer(2) Understand the concepts of IC design technology(3) Understand the implementation of logic using Fixed Function IC Technology, Full Custom ASIC Technology, and Semi-Custom ASIC Technology(4) Understand the advantages and disadvantages of implementation of logic using Fixed Function IC Technology, Full Custom ASIC Technology, and Semi-Custom ASIC Technology(5) Understand the concept of implementation of logic in PLDs(6) Understand the concept of implementation of logic in FPGA(7) Understand the IC design flow(8) Understand the role of HDL in system design(9) Understand the concepts of various Verilog language constructs(10) Understand various operators and their uses in Verilog coding(11) Understand how to use Xilinx software for writing a Verilog code(12) Understand how to use Xilinx software for simulating a Verilog code(13) Understand how to use Xilinx software for implementing a Verilog code(14) Implement combinational logic by using behavioral modeling style(15) Implement combinational logic by using dataflow modeling style(16) Implement combinational logic by using structural modeling style(17) Implement sequential logic by using behavioral modeling style(18) Implement sequential logic by using dataflow modeling style(19) Implement sequential logic by using structural modeling style(20) Implement logic by using mos transistors Overview Section 1: IC Design Technology Lecture 1 Design Metrics Lecture 2 Fixed Function IC Technology Lecture 3 Full Custom ASIC Technology Lecture 4 Semi-Custom ASIC Technology Lecture 5 HDL Role in System Design Lecture 6 PLD Technology (PLA) Lecture 7 PLD Technology (PAL) Lecture 8 FPGA (Architecture) Lecture 9 FPGA (Logic Implementation Examples) Section 2: Introduction to Verilog and Xilinx Software Lecture 10 Introduction to Verilog Lecture 11 Level of Abstraction Lecture 12 Introduction to Xilinx Software Lecture 13 Data Types (Net Types) Lecture 14 Data Types (Register Types) Lecture 15 Operator (Bitwise operators) Lecture 16 Operator (Logical & Reduction) Lecture 17 Operator (Arithmetic, Relational & Shift) Lecture 18 Operator (Concatenation, Conditional & Replication) Section 3: Introduction to different level of modeling Lecture 19 Introduction to Structure Level Modeling Lecture 20 Introduction to Behavioural Level Modeling Lecture 21 Introduction to Dataflow Level Modeling Section 4: Testbench Lecture 22 Test Bench-(Part I) Lecture 23 Test Bench -(Part II) Lecture 24 Test Bench-(Part III) Section 5: Structure Modeling Lecture 25 Structure Modeling (2 to 1 Multiplexer) Lecture 26 Structure Modeling (2 to 4 Decoder) Lecture 27 Structure Modeling (3-Bit Adder) Part - I Lecture 28 Structure Modeling (3-Bit Adder) Part - II Section 6: Behavioural Modeling Lecture 29 Procedural Statements Lecture 30 Sequential Statements (if-else) Part-I Lecture 31 Sequential Statements (if-else) Part-II Lecture 32 Sequential Statements (if-else) Part-III Lecture 33 2 to 4 Decoder using if-else Statement Lecture 34 Comparator using "if-else" Statement Lecture 35 Software demonstration of Comparator Lecture 36 2 to 1 Multiplexer using "case" Statement Lecture 37 4 to 1 Multiplexer using "case" Statement Lecture 38 2 to 4 Decoder using "case" Statement Lecture 39 1 Bit Comparator using "case" Statement Lecture 40 BCD to 7 Segment Decoder using "case" Statement Lecture 41 Sequential Statements - (loop) Section 7: Behaviourl Model - Sequential Circuits Lecture 42 Verilog code of D Flip Flop Lecture 43 Verilog code of JK Flip Flop Lecture 44 Verilog code of T Flip Flop Lecture 45 Verilog code of 3 Bit Counter Lecture 46 Parallel In Parallel Out Register Lecture 47 Serial In Parallel Out Register Lecture 48 Serial In Serial Out Register Section 8: Multiple Always Block Lecture 49 Multiple always block - (Example) Lecture 50 Multiple always block - (D Flip Flop) Lecture 51 Multiple always block - (2 to 4 Decoder) Section 9: Blocking and Non-blocking Statements Lecture 52 Blocking Statement Lecture 53 Non-Blocking Statement Section 10: Few Examples of Combinational Circuits Lecture 54 Verilog Model of Full Subtractor Lecture 55 Binary to Gray Converter Lecture 56 Gray to Binary Converter Lecture 57 Verilog Code of 1 to 2 Demultiplexer Lecture 58 Priority Encoder Section 11: Switch Level Modeling Lecture 59 "cmos" Switch (Part I) Lecture 60 "cmos" Switch (Part II) Lecture 61 "cmos" Switch (Part III) Lecture 62 "cmos" Switch (Part IV) Students who are interested to write and simulate verilog codes written for combinational and sequential circuits Hidden Content Give reaction to this post to see the hidden content. Download from RapidGator Hidden Content Give reaction to this post to see the hidden content. Download from DDownload Hidden Content Give reaction to this post to see the hidden content. Link to comment
Recommended Posts
Please sign in to comment
You will be able to leave a comment after signing in
Sign In Now